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8XC196KD 8XC196KD20 COMMERCIAL CHMOS MICROCONTROLLER
87C196KD 32 Kbytes of On-Chip OTPROM 83C196KD 32 Kbytes of ROM
Y Y Y Y Y Y Y Y Y Y Y
16 MHz and 20 MHz Available 1000 Byte Register RAM Register-to-Register Architecture 28 Interrupt Sources 16 Vectors Peripheral Transaction Server 1 4 ms 16 x 16 Multiply (20 MHz) 2 4 ms 32 16 Divide (20 MHz) Powerdown and Idle Modes Five 8-Bit I O Ports 16-Bit Watchdog Timer Dynamically Configurable 8-Bit or 16-Bit Buswidth
Y Y Y Y Y Y Y
Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Up Down Counter with Capture 3 Pulse-Width-Modulated Outputs Four 16-Bit Software Timers 8- or 10-Bit A D Converter with Sample Hold HOLD HLDA Bus Protocol OTP One-Time Programmable Version
Y Y
The 8XC196KD 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family The 8XC196KD is an enhanced 80C196KC device with 1000 bytes RAM 16 MHz operation and an optional 32 Kbytes of ROM EPROM Intel's CHMOS III process provides a high performance processor along with low power consumption The 8XC196KD has a maximum guaranteed frequency of 16 MHz The 8XC196KD20 has a maximum guaranteed frequency of 20 MHz Unless otherwise noted all references to the 8XC196KD also refer to the 8XC196KD20 Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the timer or up down counter
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1994
Order Number 272145-003
8XC196KD 8XC196KD20
272145 - 1
Figure 1 8XC196KD Block Diagram
87C196KD ENHANCED FEATURE SET OVER THE 87C196KC
1 The 87C196KD has twice the RAM and twice the OTPROM space of the 87C196KC 2 The vertical windowing scheme has been extended to allow all 1000 bytes of register RAM to be windowed into the lower register file
IOC3 (0CH HWIN1 READ WRITE)
272145 - 2
NOTE RSV Reserved bits must be e 0
Figure 2 87C196KD New SFR Bit (CLKOUT Disable)
2
8XC196KD 8XC196KD20
8XC196KD VERTICAL WINDOWING MAP
Table 1 128-Byte Windows Address to Remap 0380H 0300H 0280H 0200H 0180H 0100H 0080H 0000H Device Series KD KD KD KD KC KD KC KD KC KD KC KD WSR Contents X001 0111B e 17H X001 0110B e 16H X001 0101B e 15H X001 0100B e 14H X001 0011B e 13H X001 0010B e 12H X001 0001B e 11H X001 0000B e 10H
Table 3 32-Byte Windows Address to Remap 03E0H 03C0H 03A0H 0380H 0360H 0340H 0320H 0300H 02E0H 02C0H 02A0H 0280H 0260H 0240H 0220H 0200H 01E0H 01C0H 01A0H 0180H 0160H 0140H 0120H 0100H 00E0H 00C0H 00A0H 0080H 0060H 0040H 0020H 0000H Device Series KD KD KD KD KD KD KD KD KD KD KD KD KD KD KD KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD WSR Contents X101 1111B e 5FH X101 1110B e 5EH X101 1101B e 5DH X101 1100B e 5CH X101 1011B e 5BH X101 1010B e 5AH X101 1001B e 59H X101 1000B e 58H X101 0111B e 57H X101 0110B e 56H X101 0101B e 55H X101 0100B e 54H X101 0011B e 53H X101 0010B e 52H X101 0001B e 51H X101 0000B e 50H X100 1111B e 4FH X100 1110B e 4EH X100 1101B e 4DH X100 1100B e 4CH X100 1011B e 4BH X100 1010B e 4AH X100 1001B e 49H X100 1000B e 48H X100 0111B e 47H X100 0110B e 46H X100 0101B e 45H X100 0100B e 44H X100 0011B e 43H X100 0010B e 42H X100 0001B e 41H X100 0000B e 40H
Window in Lower Register File 80H-FFH
Table 2 64-Byte Windows Address to Remap 03C0H 0380H 0340H 0300H 02C0H 0280H 0240H 0200H 01C0H 0180H 0140H 0100H 00C0H 0080H 0040H 0000H Device Series KD KD KD KD KD KD KD KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD KC KD WSR Contents X010 1111B e 2FH X010 1110B e 2EH X010 1101B e 2DH X010 1100B e 2CH X010 1011B e 2BH X010 1010B e 2AH X010 1001B e 29H X010 1000B e 28H X010 0111B e 27H X010 0110B e 26H X010 0101B e 25H X010 0100B e 24H X010 0011B e 23H X010 0010B e 22H X010 0001B e 21H X010 0000B e 20H
Window in Lower Register File C0H-FFH
Window in Lower Register File E0H - FFH
3
8XC196KD 8XC196KD20
PROCESS INFORMATION
This device is manufactured on PX29 5 or PX29 9 a CHMOS III process Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook Order Number 210997
Table 5 8XC196KD Memory Map Description External Memory or I O Internal ROM OTPROM or External Memory (Determined by EA) Reserved Must contain FFH (Note 5) PTS Vectors Upper Interrupt Vectors ROM OTPROM Security Key Reserved Must contain FFH (Note 5) Reserved Must Contain 20H (Note 5) CCB Reserved Must contain FFH (Note 5) Address 0FFFFH 0A000H 9FFFH 2080H 207FH 205EH 205DH 2040H 203FH 2030H 202FH 2020H 201FH 201AH 2019H 2018H 2017H 2014H 2013H 2000H 1FFFH 1FFEH 1FFDH 0400H 03FFH 0018H 0017H 0000H
272145 - 19
EXAMPLE N87C196KD20 is 68-Lead PLCC OTPROM 20 MHz For complete package dimensional data refer to the Intel Packaging Handbook (Order Number 240800) NOTE 1 EPROMs are available as One Time Programmable (OTPROM) only
Lower Interrupt Vectors Port 3 and Port 4 External Memory 1000 Bytes Register RAM (Note 1)
Figure 3 The 8XC196KD Family Nomenclature Table 4 Thermal Characteristics Package Type PLCC QFP SQFP ija 35 C W 56 C W 68 C W ijc 13 C W 12 C W 15 5 C W
CPU SFR's (Notes 1 3)
All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology
NOTES 1 Code executed in locations 0000H to 03FFH will be forced external 2 Reserved memory locations must contain 0FFH unless noted 3 Reserved SFR bit locations must contain 0 4 Refer to 8XC196KC for SFR descriptions 5 WARNING Reserved memory locations must not be written or read The contents and or function of these locations may change with future revisions of the device Therefore a program that relies on one or more of these locations may not function properly
4
8XC196KD 8XC196KD20
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Figure 4 68-Pin PLCC Package
5
8XC196KD 8XC196KD20
272145 - 4
NOTE N C means No Connect (do not connect these pins)
Figure 5 80-Pin QFP Package
6
8XC196KD 8XC196KD20
272145 - 20
NOTE N C means No Connect (do not connect these pins)
Figure 6 80-Pin SQFP Package
7
8XC196KD 8XC196KD20
PIN DESCRIPTIONS
Symbol VCC VSS VREF Main supply voltage (5V) Digital circuit ground (0V) There are multiple VSS pins all of which must be connected Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Timing pin for the return from powerdown circuit This pin also supplies the programming voltage on the EPROM device Input of the oscillator inverter and of the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency of CLKOUT is frequency Reset input and open drain output Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an 8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus A positive transition causes a vector through 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch Input for memory select (External Access) EA equal high causes memory accesses to locations 2000H through 9FFFH to be directed to on-chip ROM EPROM EA equal low causes accesses to those locations to be directed to off-chip memory Also used to enter programming mode Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a signal to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is activated only during external memory writes Bus High Enable or Write High output to external memory as selected by the CCR BHE will go low for external writes to the high byte of the data bus WRH will go low for external writes where an odd byte is being written BHE WRH is activated only during external memory writes Ready input to lengthen external memory cycles for interfacing to slow or dynamic memory or for bus sharing When the external memory is not being used READY has no effect Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them (HSI 2 and HSI 3) are shared with the HSO Unit Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSI 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the HSI Unit the oscillator Name and Function
ANGND VPP XTAL1 XTAL2 CLKOUT RESET BUSWIDTH
NMI INST
EA
ALE ADV
RD WR WRL
BHE WRH
READY
HSI HSO
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8XC196KD 8XC196KD20
PIN DESCRIPTIONS (Continued)
Symbol Port 0 Port 1 Port 2 Ports 3 and 4 HOLD HLDA BREQ PMODE PACT PALE Name and Function 8-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter 8-bit quasi-bidirectional I O port 8-bit multi-functional port All of its pins are shared with other functions in the 8XC196KD Pins 2 6 and 2 7 are quasi-bidirectional 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Bus Hold input requesting control of the bus Bus Hold acknowledge output indicating release of the bus Bus Request output activated when the bus controller has a pending external memory cycle Determines the EPROM programming mode A low signal in Auto Programming mode indicates that programming is in process A high signal indicates programming is complete A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address command information (input to slave) A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data (input to slave) A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly Cummulative Program Output Verification Pin is high if all locations have programmed correctly since entering a programming mode Auto Increment Active low input enables the auto increment mode Auto increment allows reading or writing sequential EPROM locations without address transactions across the PBUS for each read or write
PROG PVER CPVER AINC
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8XC196KD 8XC196KD20
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin to VSS Except EA and VPP Voltage from EA or VPP to VSS or ANGND Power Dissipation
b 55 C to a 125 C b 65 C to a 150 C b 0 5V to a 7 0V(1) b 0 5V to a 13 00V
NOTICE This data sheet contains information on products in the sampling and initial production phases of development It is valid for the devices indicated in the revision history The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
1 5W(2)
NOTES 1 This includes VPP and EA on ROM or CPU only devices 2 Power dissipation is based on package heat transfer limitations not device power consumption
OPERATING CONDITIONS
Symbol TA VCC VREF ANGND FOSC FOSC Description Ambient Temperature Under Bias Commercial Temp Digital Supply Voltage Analog Supply Voltage Analog Ground Voltage Oscillator Frequency (8XC196KD) Oscillator Frequency (8XC196KD20) Min 0 4 50 4 00 VSS b 0 4 8 8 Max
a 70
Units C V V V(1) MHz MHz
5 50 5 50 VSS a 0 4 16 20
NOTE 1 ANGND and VSS should be nominally at the same potential
DC CHARACTERISTICS
Symbol VIL VIH VHYS VIH1 VIH2 VOL Input Low Voltage
(Over Specified Operating Conditions) Min
b0 5
Description
Max 08 VCC a 0 5 VCC a 0 5 VCC a 0 5 03 0 45 15 08
Units V V mV V V V V V V V V V V V V
Test Conditions
Input High Voltage (Note 1) Hysteresis on RESET Input High Voltage on XTAL 1 Input High Voltage on RESET Output Low Voltage
0 2 VCC a 1 0 300 0 7 VCC 22
VCC e 5 0V
IOL e 200 mA IOL e 2 8 mA IOL e 7 mA IOL e a 0 4 mA IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 mA IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA
VOL1 VOH
Output Low Voltage in RESET on P2 5 (Note 2) Output High Voltage (Standard Outputs) (Note 4) Output High Voltage (Quasi-bidirectional Outputs) (Note 3) VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 3 VCC b 0 7 VCC b 1 5
VOH1
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8XC196KD 8XC196KD20
DC CHARACTERISTICS
Symbol IOH1
(Over Specified Operating Conditions) (Continued) Min
b0 8
Description Logical 1 Output Current in Reset on P2 0 Do not exceed this or device may enter test modes Logical 0 Input Current in Reset on P2 0 Maximum current that must be sunk by external device to ensure test mode entry Logical 1 Input Current Maximum current that external device must source to initiate NMI Input Leakage Current (Std Inputs) (Note 5) Input Leakage Current (Port 0) 1 to 0 Transition Current (QBD Pins) Logical 0 Input Current (QBD Pins) AD Bus in Reset Active Mode Current in Reset (8XC196KD) Active Mode Current in Reset (8XC196KD20) Idle Mode Current (8XC196KD) Idle Mode Current (8XC196KD20) Powerdown Mode Current A D Converter Reference Current Reset Pullup Resistor Pin Capacitance (Any Pin to VSS)
Typ
Max
Units mA
Test Conditions VIH e VCC b 1 5V
IIL2
b 12 0
mA
VIN e 0 45V
IIH1
a 200
mA
VIN e 2 4V
ILI ILI1 ITL IIL IIL1 ICC ICC IIDLE IIDLE IPD IREF RRST CS
g10
mA mA mA mA mA mA mA mA mA mA mA X pF
0 k VIN k VCC b 0 3V 0 k VIN k VREF VIN e 2 0V VIN e 0 45V VIN e 0 45V XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V XTAL1 e 20 MHz VCC e VPP e VREF e 5 5V XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V XTAL1 e 20 MHz VCC e VPP e VREF e 5 5V VCC e VPP e VREF e 5 5V VCC e VPP e VREF e 5 5V VCC e 5 5V VIN e 4 0V
g3
b 650 b 70 b 70
65 80 17 21 8 2 6K
75 92 25 30 15 5 65K 10
NOTES 1 All pins except RESET and XTAL1 2 Violating these specifications in Reset may cause the part to enter test modes 3 QBD (Quasi-bidirectional) pins include Port 1 P2 6 and P2 7 4 Standard Outputs include AD0-15 RD WR ALE BHE INST HSO pins PWM P2 5 CLKOUT RESET Ports 3 and 4 TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open-drain outputs 5 Standard Inputs include HSI pins READY BUSWIDTH RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 6 Maximum current per pin must be externally limited to the following values if VOL is held above 0 45V or VOH is held below VCC b 0 7V IOL on Output pins 10 mA IOH on quasi-bidirectional pins self limiting IOH on Standard Output pins 10 mA 7 Maximum current per bus pin (data and control) during normal operation is g3 2 mA 8 During normal (non-transient) conditions the following total current limits apply IOH is self limiting Port 1 P2 6 IOL 29 mA IOH 26 mA HSO P2 0 RXD RESET IOL 29 mA IOL 13 mA IOH 11 mA P2 5 P2 7 WR BHE IOH 52 mA AD0 - AD15 IOL 52 mA IOH 13 mA RD ALE INST-CLKOUT IOL 13 mA
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8XC196KD 8XC196KD20
272145 - 5
ICC Max e 4 13 c Frequency a 9 mA ICC Typ e 3 50 c Frequency a 9 mA IIDLE Max e 1 25 c Frequency a 5 mA IIDLE Typ e 0 88 c Frequency a 3 mA NOTE Frequencies below 8 MHz are shown for reference only no testing is performed
Figure 7 ICC and IIDLE vs Frequency
AC CHARACTERISTICS
For use over specified operating conditions Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 20 MHz The system must meet these specifications to work with the 80C196KD Symbol TAVYV TYLYH TCLYX TLLYX TAVGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRXDX Description Address Valid to READY Setup Non READY Time READY Hold after CLKOUT Low READY Hold after ALE Low Address Valid to Buswidth Setup Buswidth Hold after CLKOUT Low Address Valid to Input Data Valid RD Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD Inactive 0 0 3 TOSC b 55 TOSC b 22 TOSC b 45 TOSC 0 TOSC b 15 Min Max 2 TOSC b 68 No upper limit TOSC b 30 2 TOSC b 40 2 TOSC b 68 Units ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 2) (Note 1) (Note 1) Notes
NOTES 1 If max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC N where N e number of wait states
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8XC196KD 8XC196KD20
AC CHARACTERISTICS
(Continued) For use over specified operating conditions Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 20 MHz
The 80C196KD will meet these specifications Symbol FXTAL FXTAL TOSC TOSC TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Description Frequency on XTAL1 (8XC196KD) Frequency on XTAL1 (8XC196KD20) I FXTAL (8XC196KD) I FXTAL (8XC196KD20) XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling Edge to ALE Rising ALE Falling Edge to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD Falling Edge RD Low to CLKOUT Falling Edge RD Low Period RD Rising Edge to ALE Rising Edge RD Low to Address Float ALE Falling Edge to WR Falling Edge CLKOUT Low to WR Falling Edge Data Stable to WR Rising Edge CLKOUT High to WR Rising Edge WR Low Period Data Hold after WR Rising Edge WR Rising Edge to ALE Rising Edge BHE INST after WR Rising Edge AD8-15 HOLD after WR Rising BHE INST after RD Rising Edge AD8-15 HOLD after RD Rising TOSC b 10 0 TOSC b 23
b5 a 15 a 25
Min 8 8 62 5 50
a 20
Max 16 20 125 125
a 110
Units MHz MHz ns ns ns ns ns ns ns ns ns
Notes (Note 1) (Note 1)
2 TOSC TOSC b 10
b5 b 20
TOSC a 15
a 15 a 15
4 TOSC TOSC b 10 TOSC b 15 TOSC b 35 TOSC b 30
a4 a 30
(Note 4)
TOSC a 10
ns ns ns ns TOSC a 25
a5
TOSC b 5 TOSC
(Note 4) (Note 2)
ns ns ns ns
(Note 4) ns ns ns TOSC a 15 ns ns ns ns ns (Note 3) (Note 3) (Note 2) (Note 4)
TOSC b 20 TOSC b 25 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 10 TOSC b 25
NOTES 1 Testing performed at 8 MHz However the device is static by design and will typically operate below 1 Hz 2 Assuming back-to-back bus cycles 3 8-Bit bus only 4 If wait states are used add 2 TOSC N where N e number of wait states
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8XC196KD 8XC196KD20
System Bus Timings
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8XC196KD 8XC196KD20
READY Timings (One Wait State)
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Buswidth Timings
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8XC196KD 8XC196KD20
HOLD HLDA TIMINGS
Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV TCLLH HOLD Setup CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid CLKOUT Low to ALE High
b 15 b 15 b 15 b 10 b5 a 15 a 15
Description
Min
a 55 b 15 b 15
Max
Units ns
Notes (Note 1)
a 15 a 15 a 15 a 20 a 15 a 15
ns ns ns ns ns ns ns ns ns
NOTE 1 To guarantee recognition at next clock
DC SPECIFICATIONS IN HOLD Description Weak Pullups on ADV RD WR WRL BHE Weak Pulldowns on ALE INST Min 50K 10K Max 250K 50K Units VCC e 5 5V VIN e 0 45V VCC e 5 5V VIN e 2 4
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8XC196KD 8XC196KD20
MAXIMUM HOLD LATENCY Bus Cycle Type Internal Execution 16-Bit External Execution 8-Bit External Execution 1 5 States 2 5 States 4 5 States
EXTERNAL CLOCK DRIVE (8XC196KD)
Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period High Time Low Time Rise Time Fall Time Min 8 62 5 20 20 10 10 Max 16 0 125 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE (8XC196KD20)
Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period High Time Low Time Rise Time Fall Time Min 8 50 17 17 8 8 Max 20 0 125 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE WAVEFORMS
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8XC196KD 8XC196KD20
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
272145 - 13 272145 - 14
NOTE Keep oscillator components close to chip and use short direct traces to XTAL1 XTAL2 and VSS When using ceramic crystals C1 e 20 pF C2 e 20 pF When using ceramic resonators consult manufacturer for recommended capacitor values
NOTE Required if TTL driver used Not needed if CMOS driver is used
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272145 - 11 AC Testing inputs are driven at 2 4V for a Logic ``1'' and 0 45V for a Logic ``0'' Timing measurements are made at 2 0V for a Logic ``1'' and 0 8V for a Logic ``0''
272145 - 12 For Timing Purposes a Port Pin is no Longer Floating when a 150 mV change from Load Voltage Occurs and Begins to Float when a 150 mV change from the Loaded VOH VOL Level occurs IOL IOH e g15 mA
EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ``T'' for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions H High L Low V X Z Valid No Longer Valid Floating Signals A Address B BHE C D G H HA CLKOUT DATA Buswidth HOLD HLDA
L BR R W X Y Q
ALE ADV BREQ RD WR WRH WRL XTAL1 READY Data Out
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8XC196KD 8XC196KD20
AC CHARACTERISTICS
SERIAL PORT TIMING Symbol TXLXL TXLXH TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
SERIAL PORT
SHIFT REGISTER MODE
SHIFT REGISTER MODE (MODE 0) Parameter Min 6 TOSC 4 TOSC b 50 4 TOSC 2 TOSC b 50 2 TOSC b 50 2 TOSC b 50 2 TOSC a 50 TOSC a 50 0 1 TOSC 2 TOSC a 50 4 TOSC a 50 Max Units ns ns ns ns ns ns ns ns ns ns
Serial Port Clock Period (BRR t 8002H) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) Serial Port Clock Period (BRR e 8001H) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) Output Data Valid to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float
WAVEFORM
SERIAL PORT
SHIFT REGISTER MODE
SERIAL PORT WAVEFORM
SHIFT REGISTER MODE (MODE 0)
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8XC196KD 8XC196KD20
A to D CHARACTERISTICS
The A D converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF
10-BIT MODE A D OPERATING CONDITIONS
Symbol TA VCC VREF ANGND TSAM TCONV FOSC FOSC
NOTE 1 The value of AD
Description Ambient Temperature Commercial Temp Digital Supply Voltage Analog Supply Voltage Analog Ground Voltage Sample Time Conversion Time Oscillator Frequency (8XC196KD) Oscillator Frequency (8XC196KD20)
TIME is selected to meet these specifications
Min 0 4 50 4 00 VSS b 0 40 10 10 80 80
Max
a 70
Units C V V V ms(1) ms(1) MHz MHz
5 50 5 50 VCC a 0 40 20 16 0 20 0
10-BIT MODE A D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin DC Input Leakage Sampling Capacitor 3
b 60 b 60
g0 1 g0 25
Typical(1)
Minimum 1024 10 0
Maximum 1024 10
g3
Units Levels Bits LSBs LSBs LSBs
Notes
0 25 g 0 5 0 25 g 0 5 10g20 0
lb 1 g3
LSBs LSBs LSBs LSBs LSB C LSB C LSB C
a2
g1
0
0 009 0 009 0 009
b 60
dB dB dB
23 2 2 4 56
750 ANGND b 0 5 0
1 2K VREF a 0 5
g3 0
X V mA pF
NOTES An ``LSB'' as used here has a value of approxiimately 5 mV (See Embedded Microcontrollers and Processors Handbook for A D glossary of terms ) 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer Break-Before-Make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 These values may be exceeded if the pin current is limited to g2 mA 6 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted 7 All conversions performed with processor in IDLE mode
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8XC196KD 8XC196KD20
8-BIT MODE A D OPERATING CONDITIONS
Symbol TA VCC VREF ANGND TSAM TCONV FOSC FOSC
NOTE 1 The value of AD
Description Ambient Temperature Commercial Temp Digital Supply Voltage Analog Supply Voltage Analog Ground Voltage Sample Time Conversion Time Oscillator Frequency (8XC196KD) Oscillator Frequency (8XC196KD20)
TIME is selected to meet these specifications
Min 0 4 50 4 00 VSS b 0 40 10 7 80 80
Max
a 70
Units C V V V ms(1) ms(1) MHz MHz
5 50 5 50 VSS a 0 40 20 16 0 20 0
8-BIT MODE A D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin DC Input Leakage Sampling Capacitor 3
b 60 b 60
g0 25 g0 5 g0 5
(Over Specified Operating Conditions) Minimum 256 8 0 Maximum 256 8
g1
Typical(1)
Units Levels Bits LSBs LSBs LSBs
Notes
0
lb 1
g1
LSBs LSBs LSBs LSBs LSB C LSB C LSB C
a1
g1
0 003 0 003 0 003
b 60
dB dB dB
23 2 2 4 56
750 VSS b 0 5 0
1 2K VREF a 0 5
g3 0
X V mA pF
NOTES An ``LSB'' as used here has a value of approximately 20 mV (See Embedded Microcontrollers and Processors Handbook for A D glossary of terms) 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer Break-Before-Make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 These values may be exceeded if pin current is limited to g2 mA 6 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted 7 All conversions performed with processor in IDLE mode
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8XC196KD 8XC196KD20
OTPROM SPECIFICATIONS OPERATING CONDITIONS
Symbol TA VCC VREF VPP VEA FOSC FOSC FOSC Description Ambient Temperature During Programming Supply Voltage During Programming Reference Supply Voltage During Programming Programming Voltage EA Pin Voltage Oscillator Frequency during Auto and Slave Mode Programming Oscillator Frequency during Run-Time Programming (8XC196KD) Oscillator Frequency during Run-Time Programming (8XC196KD20) Min 20 45 45 12 25 12 25 60 60 60 Max 30 55 55 12 75 12 75 80 16 0 20 0 Units C V(1) V(1) V(2) V(2) MHz MHz MHz
NOTES 1 VCC and VREF should nominally be at the same voltage during programming 2 VPP and VEA must never exceed the maximum specification or the device may be damaged 3 VSS and ANGND should nominally be at the same potential (0V) 4 Load capacitance during Auto and Slave Mode programming e 150 pF
AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)
Symbol TSHLL TLLLH TAVLL TLLAX TPLDV TPHDX TDVPL TPLDX TPLPH(1) TPHLL TLHPL TPHPL TPHIL TILIH TILVH TILPL TPHVL Description Reset High to First PALE Low PALE Pulse Width Address Setup Time Address Hold Time PROG Low to Word Dump Valid Word Dump Data Hold Data Setup Time Data Hold Time PROG Pulse Width PROG High to Next PALE Low PALE High to PROG Low PROG High to Next PROG Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 0 400 50 220 220 220 0 240 50 170 220 Min 1100 50 0 100 50 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
NOTE 1 This specification is for the Word Dump Mode For programming pulses use the Modified Quick Pulse Algorithm
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8XC196KD 8XC196KD20
DC OTPROM PROGRAMMING CHARACTERISTICS
Symbol IPP Description VPP Supply Current (When Programming) Min Max 100 Units mA
NOTE Do not apply VPP until VCC is stable and within specifications and the oscillator clock has stabilized or the device may be damaged
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
272145 - 16
NOTE P3 0 must be high (``1'')
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8XC196KD 8XC196KD20
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
272145 - 17
NOTE P3 0 must be low (``0'')
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT
272145 - 18
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8XC196KD 8XC196KD20
3 Changed QFP Package iJA to 56 C W from 42 C W 4 Changed VHYS to 300 mV from 150 mV 5 Changed ICC Typical specification at 16 MHz to 65 mA from 50 mA 6 Changed ICC Maximum specification at 16 MHz to 75 mA from 70 mA 7 Changed IIDLE Typical specification to 17 mA from 15 mA 8 Changed IIDLE Maximum specification to 25 mA from 30 mA 9 Changed IPD Typical specification to 8 mA from 15 mA 10 Added IPD Maximum specification 11 Changed TCLDV Maximum specification to TOSC b 45 from TOSC b 50 12 Changed TLLAX Minimum specification to TOSC b 35 from TOSC b 40 13 Changed TCHWH Minimum specification to b 5 from b 10 14 Changed TRHAX Minimum specification to TOSC b 25 from TOSC b 30 15 Changed THALAZ Maximum specification to a 15 from a 10 16 Changed THALBZ Maximum specification to a 20 from a 15 17 Added THAHBV Maximum specification 18 Changed TSAM for 10-bit mode to 1 ms from 3 ms 19 Changed TSAM for 8-bit mode to 1 ms from 2 ms 20 Changed IIH1 test condition to VIN e 2 4V from 5 5V 21 Changed IIH1 maximum specification to a 200 mA from a 100 mA 22 Removed NMI from list of standard inputs 23 Updated ICC and IIDLE vs frequency graph 24 Updated note under DC EPROM Programming Characteristics 25 Changed ILI1 maximum specification to b 12 mA from b 6 mA
8XC196KC TO 8XC196KD DESIGN CONSIDERATIONS
1 Memory Map The 8XC196KD has 1024 bytes of RAM SFRs and 32K of OTPROM The extra 512 bytes of RAM reside in locations 0200H to 03FFH and the extra 16 Kbytes of OTPROM reside in locations 6000H to 9FFFH On the 87C196KC these locations are always external so KC code may have to be modified to run on the KD 2 The vertical window scheme has been extended to include all on-chip RAM 3 IOC3 1 controls the CLKOUT signal This bit must be 0 to enable CLKOUT 4 The 87C196KD has a different autoprogramming algorithm to support 32K of on-chip OTPROM
8XC196KD ERRATA
1 83C196KD can possibly miss interrupts on P0 7 See techbit MC0893
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a ``D'' and ``E'' at the end of the topside tracking number Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following are important differences between the 272145-002 and 272145-003 data sheets 1 IIL1 specification (logic 0 input current in reset) was misnamed It is renamed IIL2 2 TLLYV and TLLGV were removed These specifications are not necessary for high-speed system designs 3 An errata with 83C196KD P0 7 EXTINT was added to the errata section The following are important differences between the 272145-001 and 272145-002 data sheets 1 Added 20 MHz specifications 2 Added 80-lead SQFP package pinout
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